1. Field of the Invention
The present disclosure generally relates to FeRAM devices, and more particularly, to a low voltage detector and method for detecting low voltage of nonvolatile ferroelectric random access memory (hereinafter, referred to as ‘FeRAM’) chips which secures safe memory cell operation in threshold voltage regions by synchronizing start and stop operation of FeRAM cells to chip activation signals.
2. Description of the Background Art
Generally, a FeRAM has the same data processing speed as a dynamic random access memory (DRAM) and retains data even when power is off. For this characteristic, the FeRAM has been highly regarded as a next generation memory device.
The FeRAM has structures similar to those of a DRAM, and uses ferroelectric material as a component of a capacitor. The FeRAM uses high residual polarization, which is a characteristic of ferroelectric material, by using.
Due to the high residual polarization, data remains unerased even if the electric field is removed.
FIG. 1 illustrates a hysteresis loop of a general ferroelectric.
As shown in FIG. 1, polarization induced by the electric field is maintained at a certain amount (i.e., “d” and “a” states) due to the presence of residual polarization (or spontaneous polarization), even if the electric field is removed.
A FeRAM cell may be used as a memory device by corresponding the “d” and “a” states to 1 and 0, respectively.
FIG. 2 illustrates a unit cell of a conventional FeRAM device.
As shown in FIG. 2, the unit cell of the conventional FeRAM device includes a bitline B/L formed in one direction, a wordline W/L formed to cross bitline B/L and a plateline P/L arranged parallel to the wordline and spaced at a predetermined interval from the wordline W/L. The unit cell also includes a NMOS transistor having a gate terminal connected to the wordline W/L and a source terminal connected to the bitline B/L, and a ferroelectric capacitor FC1 connected between the drain terminal of the NMOS transistor and the plateline P/L.
The data input/output operation of the conventional FeRAM device is now described as follows.
FIG. 3A is a timing chart illustrating a write mode operation of a general FeRAM device, and FIG. 3B is a timing chart illustrating a read mode operation of a general FeRAM device.
Referring to FIG. 3A, if an externally applied chip enable signal CSBPAD is activated from ‘high’ to ‘low’, a write enable signal is transited from ‘high’ to ‘low’, and the writing mode starts.
Subsequently, if an address is decoded starts in the write mode, the corresponding wordline W/L transits from ‘low’ to ‘high’ to select the cell.
During the interval wherein the wordline W/L maintains a ‘high’ state, a ‘high’ signal of a predetermined period and a ‘low’ signal of a predetermined period are selectively applied to a corresponding plateline P/L. In order to write binary logic values ‘1’ or ‘0’ in the selected cell, ‘high’ or ‘low’ signals synchronized to the write enable signal WEBPAD are applied to a corresponding bitline B/L.
As shown in the following Table 1, during the period wherein a ‘high’ signal is applied to a wordline W/L, when a ‘high’ signal is applied to the bitline B/L and a ‘low’ signal is applied to the plateline P/L, a logic value ‘1’ is written in the ferroelectric capacitor FC1. When a ‘low’ signal is applied to the bitline B/L and a ‘high’ signal is applied to the plateline P/L, a logic value ‘0’ is written in the ferroelectric capacitor FC1.
TABLE 1P/LW/L:HHLB/LHX1L0XReferring to FIG. 3B, If an externally applied chip enable signal CSBPAD is activated from ‘high’ to ‘low’, all of the bitlines become equipotential to low voltage by an equalizer signal before a corresponding wordline is selected.Then, after each bitline becomes inactive, an address is decoded. A wordline corresponding to the decoded address is transited from the low signal to the high signal, to enable a selected cell.
A ‘high’ signal is applied to a corresponding plateline of the selected cell to destroy a data Qs corresponding to a logic value ‘1’ stored in the ferroelectric memory cell. If a logic value ‘0’ is stored in the ferroelectric memory cell, its corresponding data Qns is not destroyed.
The destroyed data or the non-destroyed data is outputted to bitlines, according to the above-described hysteresis loop characteristics, so that a sense amplifier senses logic values ‘1’ or ‘0’.
In other words, as shown in the hysteresis loop of FIG. 1, the state moves from the ‘d’ to ‘f’ when the data is destroyed while the state moves from ‘a’ to ‘f’ when the data is not destroyed. The logic value ‘1’ is output in case the data is destroyed, while the logic value ‘0’ is output in case the data is not destroyed.
After the sense amplifier amplifies the data, the data should be recovered into the original data. Accordingly, the plateline P/L becomes inactive from ‘high’ to ‘low’ during the interval where the ‘high’ signal is applied to the corresponding wordline W/L.
In a system using the above-described FeRAM, a system controller outputs a chip enable signal CSBPAD as a control signal into a FeRAM chip. A memory device in the memory chip generates a chip internal control signal CICS for operating a memory cell of a chip according to the chip enable signal CSBPAD to read/write data from/to the memory. The data is transferred to system controller via a data bus.
In the system using the nonvolatile memory, the system controller may have an operation voltage different from that of the FeRAM device.
When the system controller has the operation voltage lower than that of the FeRAM device, the system controller may generate a normal control signal and output it into the memory device, even through power voltage abnormally drops. In this case, the FeRAM device may not operate normally while the system controller operates normally. In the FeRAM device, data is read by destroying data stored in a cell. When the power voltage abnormally drops, the destroyed data in the read operation may not be recovered, by the read cycle is finished.
Accordingly, methods for conserving data during the read operation have been required in the FeRAM device. For the method for conserving data, a method using a low voltage detection circuit is provided.
FIG. 4 is a low voltage detection circuit diagram showing a conventional FeRAM device.
The low voltage detection circuit comprises a PMOS transistor T1, a NMOS transistor T2, a NMOS transistor T3 and a PMOS transistor T4. The PMOS transistor T1 and the NMOS transistor T2 are in series connected between a power voltage VCC and a ground voltage VSS, and have a common gate. The NMOS transistor T3 connected between a node A and a ground voltage VSS is controlled by output voltage of the PMOS transistor T1. The PMOS transistor T4 is connected between the node A and the power voltage VCC and has a gate terminal connected to the ground voltage VSS.
Additionally, the low voltage detection circuit comprises a first inverter INV1 for inverting an output voltage of the NMOS transistor T3, a second inverter INV2 for inverting an output signal of the first inverter INV1 and a third inverter INV3 for inverting an output signal of the second inverter INV2 to output a first output signal PONF1.
Further, the low voltage detection circuit comprises a fourth inverter INV4, connected in parallel to the first inverter INV1, for inverting an output voltage of the NMOS transistor T3, a fifth inverter INV5 for inverting an output signal of the fourth inverter INV4, a PMOS transistor T5 controlled by an output signal of the fifth inverter INV5 and connected between a power voltage terminal and an output terminal of the fourth inverter INV4, and a sixth inverter INV6 for inverting an output signal of the fifth inverter INV5 to output a second output signal PONF2.
FIG. 5 is a timing diagram showing relations between a chip enable signal CSBPAD applied externally and a control signal of an internal FeRAM device (chip internal control signal CICS) when a power voltage VCC falls from a normal voltage to a low voltage.
FIG. 6 is a timing diagram showing relations between the chip enable signal CSBPAD and the chip internal control signal CICS when the power voltage VCC rises from the low voltage to the normal voltage.
As shown in FIG. 5, when the power voltage falls below a predetermined level, the low voltage detection circuit senses the of the to a low level.
A predetermined period Twb is passed after the first output signal PONF1 is transited to the low level, and then the low voltage detection circuit transits a second output signal PONF2 to the low level.
According to combination of the first output signal PONF1 and the second output signal PONF2, the chip internal control signal CICS is maintained at the high level for a predetermined period Twb from a detection point of low voltage, and then is transited to the low level.
This operation is performed to secure a period for recovering data when the power voltage VCC falls at a low level.
On the other hand, as shown in FIG. 6, when the power voltage VCC rises over the predetermined level, the low voltage detection circuit senses the voltage variation and transits both a first output signal PONF1 and a second output signal PONF2 from a low to a high level.
Referring to FIG. 6, the chip internal control signal CICS is transited to a high level as soon as the power voltage VCC rises over the predetermined level. Accordingly, a normal read cycle waveform is not generated.
In order to prevent the problem, there may be a method of delaying one of the two output signals PONF1 or PONF2 may be delayed lest the first output signal PONF1 and the second output signal PONF2 should be transited simultaneously. However, according to the method, a corresponding cycle may be delayed to affect a system operation. As a result, the above-described problems may not be solved by delaying a signal of two output signals PONF1 and PONF2.
The conventional low voltage detection circuit generates output signals PONF1 and PONF2 by using a voltage level of power voltage VCC regardless of an externally applied chip enable signal CSBPAD.
Here, a read cycle may be fully secured to recover the destroyed data when the power voltage falls from the normal to the low voltage. Accordingly, when the power voltage rises the low voltage to the normal voltage, the read cycle has an abnormal cycle time and moves to the next cycle without recovering the destroyed data during the read operation. As a result, the destroyed data may not be safely recovered.